The present invention relates to a method of fabricating a semiconductor memory device and, more particularly, to a method of fabricating a semiconductor memory device, which can prevent electron migration within a charge trap layer.
A semiconductor memory device can be largely classified into a volatile memory device, which retains its data only when voltage is applied thereto, but loses its data when the application of voltage thereto is stopped, and a non-volatile memory device that retains its data even when the application of voltage is stopped. Of them, a non-volatile memory device has been in the spotlight because it retains its data even after the application of power is stopped. Active research has now been made on the non-volatile memory device.
A flash memory device is a representative one of the non-volatile memory devices. Recently, the size of the flash memory device becomes very small and the capacity thereof has greatly increased.
The flash memory device is described below in more detail.
A general flash memory device has a structure in which a tunnel insulating layer along which electrons are moved, a floating gate for storing data therein, a dielectric layer for preventing the leakage of charges, and a control gate for transferring voltage are sequentially stacked over a semiconductor substrate.
Meanwhile, a flash memory device that has recently been developed has a structure in which a tunnel insulating layer along which electrons are moved, a charge trap layer which traps charges and is formed from insulating material, a blocking layer for preventing trapped charges from leaking to a control gate, and the control gate for transferring voltage are sequentially stacked.
A conventional flash memory device, including the charge trap layer, is fabricated by first forming a low voltage NMOS transistor (LVN) and a high voltage NMOS transistor (HVN), which are used in a peri circuit, and then forming a memory cell to be used as a storage medium. However, in this memory cell formed according to the above sequence, charge trap layers used as trap layers of electrons are not isolated in the direction of a string in view of the manufacturing process. This is because electrons are trapped in the charge trap layer only when voltage is applied from the control gate and the trapped electrons are rarely moved unless external voltage is applied, in terms of the charge trap layer.
However, if a program operation is performed on a selected memory cell, electrons trapped in a memory cell adjacent to the selected memory cell can be moved through the charge trap layer due to a high program voltage.
In particular, the electron trap rate of the charge trap layer does not exceed about 70% when compared with the floating gate. Accordingly, the threshold voltage may be changed due to a trap characteristic that is short of about 30%.
Due to this trap characteristic of the charge trap layer, at the time of a program operation, electrons of an unselected memory cell move to a neighboring isolation layer or in the direction of a selected memory cell, which may change the threshold voltage. It may degrade a retention characteristic, that is, a charge retention capability. Consequently, the threshold voltage of a programmed memory cell is lowered as much as the amount of electrons that have exited, so that program efficiency can be lowered.